The NXP i.MX93 CPU has two 10/100/1000 Ethernet MAC.

On the ConnectCore 93 Development Kit:

  • Ethernet port 1 is connected to a 10/100/1000 Marvell 88E1512-A0-NNP2I000 PHY.

  • Ethernet port 2 is connected to a 10/100/1000 Marvell 88E1512-A0-NNP2I000 PHY.

Kernel configuration

You can manage the Ethernet driver and PHY Device support through the following kernel configuration options:

  • FEC Ethernet controller (of ColdFire and some i.MX CPUs) (CONFIG_FEC)

  • PHY device support for Marvell (88E1XXX) (CONFIG_MARVELL_PHY)

  • NXP IMX8 DWMAC support (CONFIG_DWMAC_IMX8)

These options are enabled as built-in on the default ConnectCore 93 kernel configuration file.

Kernel driver

The driver for the Ethernet interface is located at:

File Description

drivers/net/ethernet/freescale/fec_main.c

i.MX FEC driver

drivers/net/phy/marvell.c

Driver for Marvel PHY 88E1XXX

drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c

NXP IMX8 DWMAC support

Device tree bindings and customization

The i.MX93 Ethernet interface device tree binding is documented at Documentation/devicetree/bindings/net/fsl,fec.yaml. The Ethernet interface is defined in the i.MX93 CPU and ConnectCore 93 Development Kit device tree files.

Example: ENET1 and ENET2 on ConnectCore 93 Development Kit

Definition of the ethernet interfaces

i.MX93 device tree
fec: ethernet@42890000 {
	compatible = "fsl,imx93-fec", "fsl,imx8mp-fec", "fsl,imx8mq-fec";
	reg = <0x42890000 0x10000>;
	interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX93_CLK_ENET1_GATE>,
		 <&clk IMX93_CLK_ENET1_GATE>,
		 <&clk IMX93_CLK_ENET_TIMER1>,
		 <&clk IMX93_CLK_ENET_REF>,
		 <&clk IMX93_CLK_ENET_REF_PHY>;
	clock-names = "ipg", "ahb", "ptp",
		      "enet_clk_ref", "enet_out";
	assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>,
			  <&clk IMX93_CLK_ENET_REF>,
			  <&clk IMX93_CLK_ENET_REF_PHY>;
	assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
				 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>,
				 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
	assigned-clock-rates = <100000000>, <250000000>, <50000000>;
	fsl,num-tx-queues = <3>;
	fsl,num-rx-queues = <3>;
	fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>;
	status = "disabled";
};

eqos: ethernet@428a0000 {
	compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a";
	reg = <0x428a0000 0x10000>;
	interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "eth_wake_irq", "macirq";
	clocks = <&clk IMX93_CLK_ENET_QOS_GATE>,
		 <&clk IMX93_CLK_ENET_QOS_GATE>,
		 <&clk IMX93_CLK_ENET_TIMER2>,
		 <&clk IMX93_CLK_ENET>,
		 <&clk IMX93_CLK_ENET_QOS_GATE>;
	clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
	assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>,
			  <&clk IMX93_CLK_ENET>;
	assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
				 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
	assigned-clock-rates = <100000000>, <250000000>;
	intf_mode = <&wakeupmix_gpr 0x28>;
	clk_csr = <0>;
	nvmem-cells = <&eth_mac2>;
	nvmem-cell-names = "mac-address";
	status = "disabled";
};

IOMUX configuration

ConnectCore 93 Development Kit device tree
&iomuxc {
[...]
	/* EQoS RGMII */
	pinctrl_eqos: eqosgrp {
		fsl,pins = <
			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0			0x57e
			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1			0x57e
			MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2			0x57e
			MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3			0x57e
			MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x5fe
			MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x57e
			MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0			0x57e
			MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1			0x57e
			MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2			0x57e
			MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3			0x57e
			MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x5fe
			MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x57e
		>;
	};

	/* EQoS MDIO */
	pinctrl_eqos_mdio: ethmdio {
		fsl,pins = <
			MX93_PAD_ENET1_MDC__ENET_QOS_MDC			0x57e
			MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO			0x57e
		>;
	};

	/* FEC RGMII */
	pinctrl_fec: fecgrp {
		fsl,pins = <
			MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0			0x57e
			MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1			0x57e
			MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2			0x57e
			MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3			0x57e
			MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC			0x5fe
			MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL		0x57e
			MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0			0x57e
			MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1			0x57e
			MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2			0x57e
			MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3			0x57e
			MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC			0x5fe
			MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL		0x57e
		>;
	};

	/* FEC MDIO */
	pinctrl_fec_mdio: fecmdiogrp {
		fsl,pins = <
			MX93_PAD_ENET2_MDC__ENET1_MDC				0x57e
			MX93_PAD_ENET2_MDIO__ENET1_MDIO				0x57e
		>;
	};

Ethernet enabling and PHY parameters

ConnectCore 93 Development Kit device tree
/ {
	aliases {
		ethernet0 = &eqos;
		ethernet1 = &fec;
	};
};

/* Ethernet EQoS */
&eqos {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_eqos>, <&pinctrl_eqos_mdio>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	status = "okay";

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;
		clock-frequency = <5000000>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
		};
	};
};

/* Ethernet MAC (ENET) */
&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>, <&pinctrl_fec_mdio>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy1>;
	fsl,magic-packet;
	status = "disabled";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		clock-frequency = <5000000>;

		ethphy1: ethernet-phy@1 {
			/* PHY ID for Marvell 88E1512 */
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
		};
	};
};

Enable the second Ethernet interface (ENET2)

The lines of ENET2 Ethernet interface are multiplexed with other functionality through a group of jumpers on the ConnectCore 93 Development Kit. Make sure the appropriate jumpers are connected when using ENET2 Ethernet on the ConnectCore 93 Development Kit.

See Hardware reference manuals for information on the jumper connections and the multiplexed functionality they select.

The default ConnectCore 93 Development Kit device tree disables the second Ethernet by default. Digi provides a pre-compiled device tree overlay to enable this interface and disable the other ones in conflict with the multiplexing. To apply this overlay, run the following command in U-Boot:

=> setenv overlays _ov_board_enet2_ccimx9-dvk.dtbo
=> saveenv

MAC address

The MAC address of the i.MX93 Ethernet interfaces are programmed in the U-Boot environment (variables ethaddr and eth1addr) on the ConnectCore 93 eMMC. The MAC address of the first Ethernet interface is also printed on the module label. U-Boot writes the MAC address in the ethaddr and eth1addr environment variables into their respective device tree eqos and fec nodes under the local-mac-address property. For more information, see Environment variables.

Ethernet user space usage

In the Linux system, the Ethernet interface is known as ethX where X is a number, starting at 0, that indicates the interface index. The Ethernet (DWMAC) driver exposes device data through the sysfs at /sys/class/net/ethX. You can use NetworkManager to configure Ethernet settings such as IP and netmask.