Ethernet

fec1: ethernet@02188000 {
	compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
	reg = <0x02188000 0x4000>;
	interrupt-names = "int0", "pps";
	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_ENET>,
		    <&clks IMX6UL_CLK_ENET_AHB>,
		    <&clks IMX6UL_CLK_ENET_PTP>,
		    <&clks IMX6UL_CLK_ENET_REF>,
		    <&clks IMX6UL_CLK_ENET_REF>;
	clock-names = "ipg", "ahb", "ptp",
			"enet_clk_ref", "enet_out";
	stop-mode = <&gpr 0x10 3>;
	fsl,num-tx-queues=<1>;
	fsl,num-rx-queues=<1>;
	fsl,magic-packet;
	fsl,wakeup_irq = <0>;
	status = "disabled";
};

fec2: ethernet@020b4000 {
	compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
	reg = <0x020b4000 0x4000>;
	interrupt-names = "int0", "pps";
	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6UL_CLK_ENET>,
		    <&clks IMX6UL_CLK_ENET_AHB>,
		    <&clks IMX6UL_CLK_ENET_PTP>,
		    <&clks IMX6UL_CLK_ENET2_REF_125M>,
		    <&clks IMX6UL_CLK_ENET2_REF_125M>;
	clock-names = "ipg", "ahb", "ptp",
			"enet_clk_ref", "enet_out";
	stop-mode = <&gpr 0x10 4>;
	fsl,num-tx-queues=<1>;
	fsl,num-rx-queues=<1>;
	fsl,stop-mode = <&gpr 0x10 4>;
	fsl,magic-packet;
	fsl,wakeup_irq = <0>;
	status = "disabled";
};

pinctrl_enet1: enet1grp {
	fsl,pins = <
		MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
		MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
		MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
		MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
		MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
		MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
		MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
		MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
	>;
};

pinctrl_enet2: enet2grp {
	fsl,pins = <
		MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
		MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
		MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
		MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
		MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
		MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
		MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
		MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
	>;
};

/*
 * The same pins GPIO1_IO6 and GPIO_IO7 are shared as the MII
 * bus of ENET1 and ENET2. If both interfaces are enabled, the
 * IOMUX of ENET2 will apply.
 * If only one interface is enabled, the IOMUX of the enabled
 * interface will apply.
 */
pinctrl_enet1_mdio: mdioenet1grp {
	fsl,pins = <
		MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
		MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
	>;
};

pinctrl_enet2_mdio: mdioenet2grp {
	fsl,pins = <
		MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
		MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
	>;
};

pinctrl_enet1_gpio: enet1gpiogrp {
	fsl,pins = <
		/* ENET1_INT */
		MX6UL_PAD_GPIO1_IO08__GPIO1_IO08	0x1b0b0
	>;
};

pinctrl_enet2_gpio: enet2gpiogrp {
	fsl,pins = <
		/* PHY reset */
		MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x0b0b0
		/* ENET2_INT */
		MX6UL_PAD_GPIO1_IO09__GPIO1_IO09	0x1b0b0
	>;
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>;
	phy-mode = "rmii";
	phy-handle = <&ethphy0>;
	phy-reset-gpios = <&mca_gpio 7 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <26>;
	digi,phy-reset-in-suspend;
	status = "okay";
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2>,
		    <&pinctrl_enet2_mdio>,
		    <&pinctrl_enet2_gpio>;
	phy-mode = "rmii";
	phy-handle = <&ethphy1>;
	phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <26>;
	digi,phy-reset-in-suspend;
	status = "okay";

	/*
	 * The MDIO bus is shared between ENET1 and ENET2. If you only want
	 * to enable ENET1, this node must be moved to fec1 node, and the
	 * pinctrl-0 of fec1 must contain the IOMUX for the MDIO bus on ENET1
	 * (pintrl_enet1_mdio).
	 */
	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			smsc,disable-energy-detect;
			reg = <0>;
		};

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			smsc,disable-energy-detect;
			reg = <1>;
		};
	};
};