The NXP i.MX8QXP CPU has two 10/100/1000 Ethernet MACs.
On the ConnectCore 8X SBC Pro:
-
Ethernet1 port is connected to a 10/100/1000 Atheros AR8031 PHY.
-
Ethernet2 port is connected to a 10/100/1000 Atheros AR8031 PHY.
Kernel configuration
You can manage the Ethernet driver and PHY Device support through the following kernel configuration options:
-
FEC Ethernet controller (of ColdFire and some i.MX CPUs) (
CONFIG_FEC
) -
PHY device support for AT803x (
CONFIG_AT803X_PHY
)
These options are enabled as built-in on the default ConnectCore 8X kernel configuration file.
Kernel driver
The driver for the Ethernet interface is located at:
File | Description |
---|---|
i.MX FEC driver |
|
Driver for Atheros 8031 PHY |
Device tree bindings and customization
The i.MX8QXP Ethernet interface device tree binding is documented at Documentation/devicetree/bindings/net/fsl,fec.yaml
.
The Ethernet interfaces are defined in the i.MX8QXP CPU and ConnectCore 8X SBC Pro device tree files.
Example: FEC1 & FEC2 on ConnectCore 8X SBC Pro
Definition of the FECs
fec1: ethernet@5b040000 {
reg = <0x5b040000 0x10000>;
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&enet0_lpcg 4>,
<&enet0_lpcg 2>,
<&enet0_lpcg 3>,
<&enet0_lpcg 0>,
<&enet0_lpcg 1>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
assigned-clock-rates = <250000000>, <125000000>;
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
power-domains = <&pd IMX_SC_R_ENET_0>;
status = "disabled";
};
fec2: ethernet@5b050000 {
reg = <0x5b050000 0x10000>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&enet1_lpcg 4>,
<&enet1_lpcg 2>,
<&enet1_lpcg 3>,
<&enet1_lpcg 0>,
<&enet1_lpcg 1>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>;
assigned-clock-rates = <250000000>, <125000000>;
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
power-domains = <&pd IMX_SC_R_ENET_1>;
status = "disabled";
};
IOMUX configuration
/* FEC shared MDIO bus */
pinctrl_fec_mdio: fecmdiogrp {
fsl,pins = <
IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020
IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
>;
};
pinctrl_fec1_gpio: fec1gpiogrp {
fsl,pins = <
/* PHY reset */
IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x06000021
/* PHY interrupt */
IMX8QXP_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 0x06000021
>;
};
pinctrl_fec1_gpio_sleep: fec1gpiosleepgrp {
fsl,pins = <
/* PHY reset */
IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x06000041
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
/*
* The SCFW of B0 defaults ENET0 domains to 2.5V:
* - VDD_ENET0_1P8_2P5_3P3
* - VDD_ENET0_VSELECT_1P8_2P5_3P3
* Turn the domains back to 1.8/3.3V detector
*/
IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0
IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061
IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000061
IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061
IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061
IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000061
IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000061
IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000061
IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061
IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061
IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061
IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000061
IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000061
>;
};
pinctrl_fec2_gpio: fec2gpiogrp {
fsl,pins = <
/* PHY reset */
IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x06000021
/* PHY interrupt */
IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x06000021
>;
};
pinctrl_fec2_gpio_sleep: fec2gpiosleepgrp {
fsl,pins = <
/* PHY reset */
IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x06000041
>;
};
pinctrl_fec2: fec2grp {
fsl,pins = <
/*
* The SCFW of B0 defaults ENET1 domain to 2.5V:
* - VDD_ESAI_SPDIF_1P8_2P5_3P3
* Turn the domain back to 1.8/3.3V detector
*/
IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060
IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060
IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060
IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060
IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060
IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060
IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060
IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060
IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060
IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060
IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060
IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060
>;
};
Ethernet enabling and PHY parameters
&fec1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_fec_mdio>,
<&pinctrl_fec1_gpio>,
<&pinctrl_fec1>;
pinctrl-1 = <&pinctrl_fec1_gpio_sleep>;
phy-mode = "rgmii-id";
phy-handle = <ðphy1>;
digi,mdio-lt-supply = <®_1v8_ext>;
phy-supply = <®_3v3_eth0>;
phy-reset-gpios = <&lsio_gpio3 18 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
digi,phy-reset-in-suspend;
fsl,magic-packet;
status = "disabled";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
at803x,eee-disabled;
at803x,vddio-1p8v;
};
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
at803x,eee-disabled;
at803x,vddio-1p8v;
};
};
};
&fec2 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_fec2_gpio>,
<&pinctrl_fec2>;
pinctrl-1 = <&pinctrl_fec2_gpio_sleep>;
phy-mode = "rgmii-id";
phy-handle = <ðphy0>;
digi,mdio-lt-supply = <®_1v8_ext>;
phy-supply = <®_3v3_eth0>;
phy-reset-gpios = <&lsio_gpio3 22 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
digi,phy-reset-in-suspend;
fsl,magic-packet;
status = "disabled";
};
MAC addresses
The MAC addresses of the i.MX8QXP Ethernet interfaces are programmed in the U-Boot environment (variables ethaddr
and eth1addr
) on the ConnectCore 8X eMMC.
The MAC address of the first Ethernet interface is also printed on the module label.
U-Boot writes the MAC addresses in the ethaddr
and ethaddr1
environment variables into their respective device tree fec
nodes under the local-mac-address
property.
For more information, see Environment variables.
Ethernet user space usage
In the Linux system, the Ethernet interfaces are known as ethX
where X is a number, starting at 0, that indicates the interface index.
The Ethernet (FEC) driver exposes device data through the sysfs at /sys/class/net/ethX
.
You can use NetworkManager to configure Ethernet settings such as IP and netmask.