The following table lists the U-Boot file associated with each ConnectCore 93 variant:

RAM size SOC revision U-Boot file U-Boot defconfig

any

A0

imx-boot-ccimx93-dvk.bin-flash_singleboot_a0

ccimx93-dvk_defconfig

A1

imx-boot-ccimx93-dvk.bin-flash_singleboot

Check your variant SOC revision and RAM size on the serial console boot log:

U-Boot SPL dub-2023.04-r3.2 (Jan 30 2024 - 10:57:23 +0000)
SOC: 0xa1009300
LC: 0x2040010
PMIC: Over Drive Voltage Mode
M33 prepare ok
Normal Boot
Trying to boot from BOOTROM
Boot Stage: Primary boot
image offset 0x0, pagesize 0x200, ivt offset 0x0
Load image from 0x4f400 by ROM_API
NOTICE:  BL31: v2.8(release):lf-6.1.55-2.2.0-0-g08e9d4eef226-dirty
NOTICE:  BL31: Built : 16:47:44, Jan 30 2024


U-Boot dub-2023.04-r3.2 (Jan 30 2024 - 10:57:23 +0000)

CPU:   i.MX93(52) rev1.1 1700 MHz (running at 1692 MHz)
CPU:   Industrial temperature grade (-40C to 105C) at 42C
Reset cause: POR (0x1)
DRAM:  992 MiB
Core:  202 devices, 29 uclasses, devicetree: separate
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
In:    serial
Out:   serial
Err:   serial
Model: Digi ConnectCore 93 Development Kit
ConnectCore 93 SOM variant 0x01: 992 MiB LPDDR4, Wi-Fi, Bluetooth
Boot:  MMC0

BuildInfo:
  - ELE firmware version 0.1.0-44880904

flash target is MMC:0
Net:   eth0: ethernet@428a0000 [PRIME]
Fastboot: Normal
Normal Boot
Hit any key to stop autoboot:  0
=>
NXP released two revisions of the SOC silicon: revision A0 and revision A1. See SOC revisions for more information.

U-Boot might show less DRAM than the nominal. This is due to elements such as the secure monitor (OP-TEE) reserving part of the memory.