Ethernet

eth1: eth1@482c0000 {
	compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.10a";
	reg = <0x482c0000 0x4000>;
	reg-names = "stmmaceth";
	interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "macirq";
	clock-names = "stmmaceth",
			"mac-clk-tx",
			"mac-clk-rx",
			"ptp_ref",
			"ethstp",
			"eth-ck";
	clocks = <&rcc CK_ETH1_MAC>,
		<&rcc CK_ETH1_TX>,
		<&rcc CK_ETH1_RX>,
		<&rcc CK_KER_ETH1PTP>,
		<&rcc CK_ETH1_STP>,
		<&rcc CK_KER_ETH1>;
	st,syscon = <&syscfg 0x3000 0xffffffff>;
	snps,mixed-burst;
	snps,pbl = <2>;
	snps,txqos = <7>;
	snps,rxqos = <7>;
	snps,axi-config = <&stmmac_axi_config_1>;
	snps,tso;
	feature-domains = <&rifsc STM32MP25_RIFSC_ETH1_ID>;
	power-domains = <&CLUSTER_PD>;
	status = "disabled";
	snps,mtl-rx-config = <&mtl_rx_setup_1>;
	snps,mtl-tx-config = <&mtl_tx_setup_1>;

	stmmac_axi_config_1: stmmac-axi-config {
		snps,wr_osr_lmt = <0x7>;
		snps,rd_osr_lmt = <0x7>;
		snps,blen = <0 0 0 0 16 8 4>;
	};

	mtl_rx_setup_1: rx-queues-config {
		snps,rx-queues-to-use = <2>;
		queue0 {};
		queue1 {};
	};

	mtl_tx_setup_1: tx-queues-config {
		snps,tx-queues-to-use = <4>;
		queue0 {};
		queue1 {};
		queue2 {};
		queue3 {};
	};
};

eth1_mdio_pins_a: eth1-mdio-0 {
	pins1 {
		pinmux = <STM32_PINMUX('F', 0, AF10)>; /* ETH_MDC */
		bias-disable;
		drive-push-pull;
		slew-rate = <2>;
	};
	pins2 {
		...
	};
};

eth1_mdio_sleep_pins_a: eth1-mdio-sleep-0 {
	pins1 {
		pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* ETH_MDC */
			 <STM32_PINMUX('F', 2, ANALOG)>; /* ETH_MDIO */
	};
};

eth1_rgmii_pins_a: eth1-rgmii-0 {
	pins1 {
		pinmux = <STM32_PINMUX('A', 15, AF10)>, /* ETH_RGMII_TXD0 */
			 <STM32_PINMUX('C', 1, AF10)>, /* ETH_RGMII_TXD1 */
			 <STM32_PINMUX('H', 10, AF10)>, /* ETH_RGMII_TXD2 */
			 <STM32_PINMUX('H', 11, AF10)>, /* ETH_RGMII_TXD3 */
			 <STM32_PINMUX('A', 13, AF10)>; /* ETH_RGMII_TX_CTL */
		bias-disable;
		drive-push-pull;
		slew-rate = <3>;
		st,io-retime = <1>;
		st,io-clk-edge = <1>;
	};
	pins2 {
		...
	};
	pins3 {
		...
	pins4 {
		pinmux = <STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */
		bias-disable;
	};
};

eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 {
	pins {
		pinmux = <STM32_PINMUX('A', 15, ANALOG)>, /* ETH_RGMII_TXD0 */
			 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_TXD1 */
			 <STM32_PINMUX('H', 10, ANALOG)>, /* ETH_RGMII_TXD2 */
			 <STM32_PINMUX('H', 11, ANALOG)>, /* ETH_RGMII_TXD3 */
			 <STM32_PINMUX('A', 13, ANALOG)>, /* ETH_RGMII_TX_CTL */
			 <STM32_PINMUX('H', 9, ANALOG)>, /* ETH_RGMII_CLK125 */
			 <STM32_PINMUX('C', 0, ANALOG)>, /* ETH_RGMII_GTX_CLK */
			 <STM32_PINMUX('F', 1, ANALOG)>, /* ETH_RGMII_RXD0 */
			 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_RXD1 */
			 <STM32_PINMUX('H', 12, ANALOG)>, /* ETH_RGMII_RXD2 */
			 <STM32_PINMUX('H', 13, ANALOG)>, /* ETH_RGMII_RXD3 */
			 <STM32_PINMUX('A', 11, ANALOG)>, /* ETH_RGMII_RX_CTL */
			 <STM32_PINMUX('A', 14, ANALOG)>; /* ETH_RGMII_RX_CLK */
	};
};

&eth1 {
	status = "okay";
	pinctrl-0 = <&eth1_rgmii_pins_a &eth1_mdio_pins_a>;
	pinctrl-1 = <&eth1_rgmii_sleep_pins_a &eth1_mdio_sleep_pins_a>;
	pinctrl-names = "default", "sleep";
	phy-mode = "rgmii-id";
	max-speed = <1000>;
	phy-handle = <&phy1_eth1>;
	snps,ext-systime;

	/* ETH1 connected to the mdio bus ETH1_MDIO */
	mdio1 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";

		phy1_eth1: ethernet-phy@0 {
			compatible = "ethernet-phy-id0141.0dd0"; /* PHY ID for Marvell 88E1512 */
			reset-gpios =  <&gpiob 2 GPIO_ACTIVE_LOW>; /* ETH1_RST */
			reset-assert-us = <1000>;
			reset-deassert-us = <2000>;
			reg = <0>;
		};
	};
};