The STMicroelectronics STM32MP25 CPU has one PCI Express (PCIe) hardware module that can either be configured to act as a root complex or a PCI Express endpoint. PCI Express is a third-generation I/O interconnect targeting low-cost, high-volume, multi-platform interconnection.
On the ConnectCore MP25 Development Kit:
-
The PCIe port is available in the PCIe mini card connector J41.
-
Three GPIOs of the ConnectCore MP25 SOM are routed to the PCIe connector:
-
GPIOA 1
: PCIe wake line (not currently supported by the driver) -
GPIOH 4
: PCIe disable line (not currently supported by the driver) -
GPIOH 5
: PCIe reset line
-
PCIe PHY (COMBOPHY) is shared with USB3DR controller. Only one protocol can be active at a time. PCIe is enabled in the default ConnectCore MP25 Development Kit device tree. |
Kernel configuration
You can manage the PCIe driver support through the kernel configuration option:
-
STMicroelectronics PCIe Controller Host Mode for STM32 MP25 (
CONFIG_PCIE_STM32
)
This option is enabled as built-in on the default ConnectCore MP25 kernel configuration file.
Kernel driver
The PCIe bus driver for the ConnectCore MP25 system-on-module is located at drivers/pci/controller/dwc/pcie-stm32.c
.
Device tree bindings and customization
The STM32MP25 PCIe interface device tree binding is documented at Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml
.
Example: PCIe (Mini card) on the ConnectCore MP25 Development Kit
Definition of the PCIe bus
pcie_ep: pcie-ep@48400000 {
compatible = "st,stm32mp25-pcie-ep", "snps,dw-pcie-ep";
num-lanes = <1>;
reg = <0x48400000 0x400000>,
<0x10000000 0x8000000>;
reg-names = "dbi", "addr_space";
st,syscfg = <&syscfg>;
clocks = <&rcc CK_BUS_PCIE>;
clock-names = "core";
resets = <&rcc PCIE_R>;
reset-names = "pcie";
phys = <&combophy PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
feature-domains = <&rifsc STM32MP25_RIFSC_PCIE_ID>;
status = "disabled";
};
pcie_rc: pcie@48400000 {
compatible = "st,stm32mp25-pcie-rc", "snps,dw-pcie";
device_type = "pci";
num-lanes = <1>;
reg = <0x48400000 0x400000>,
<0x10000000 0x10000>;
reg-names = "dbi", "config";
st,syscfg = <&syscfg>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "aer_msi", "pme_msi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0 0x10010000 0x10010000 0 0x10000>,
<0x02000000 0 0x10020000 0x10020000 0 0x7fe0000>,
<0x42000000 0 0x18000000 0x18000000 0 0x8000000>;
bus-range = <0x00 0xff>;
clocks = <&rcc CK_BUS_PCIE>;
clock-names = "core";
resets = <&rcc PCIE_R>;
reset-names = "pcie";
phys = <&combophy PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
msi-parent = <&v2m0>;
feature-domains = <&rifsc STM32MP25_RIFSC_PCIE_ID>;
power-domains = <&CLUSTER_PD>;
status = "disabled";
};
PCIe as root complex (RC) on the ConnectCore MP25 Development Kit
&combophy {
clocks = <&rcc CK_BUS_USB3PCIEPHY>, <&rcc CK_KER_USB3PCIEPHY>, <&pad_clk>;
clock-names = "apb-clk", "ker-clk", "pad-clk";
status = "okay";
};
[...]
&pcie_ep {
reset-gpios = <&gpioh 5 GPIO_ACTIVE_LOW>;
/* DIGI - Not supported by ST driver */
/*disable-gpio = <&gpioh 4 GPIO_ACTIVE_LOW>;*/
/*wake-gpio = <&gpioa 1 GPIO_ACTIVE_LOW>;*/
status = "disabled";
};
&pcie_rc {
reset-gpios = <&gpioh 5 GPIO_ACTIVE_LOW>;
/* DIGI - Not supported by ST driver */
/*disable-gpio = <&gpioh 4 GPIO_ACTIVE_LOW>;*/
/*wake-gpio = <&gpioa 1 GPIO_ACTIVE_LOW>;*/
vdd3v3-supply = <®_3v3_board>;
vdd1v5-supply = <&scmi_ldo6>;
status = "okay";
};