The NXP i.MX8QXP CPU provides a set of one-time programmable bits (eFuses) organized in a fuse array. The fuse array is available in 1, 2, 4, 8 and 16K bits.
| These bits can be blown just once. Programming them is an irreversible operation. |
Kernel configuration
You can manage the OTP support through the following kernel configuration options:
-
NXP NVMEM On-Chip OTP Memory support (CONFIG_NVMEM_IMX_OCOTP)
-
NXP NVMEM SCU On-Chip OTP memory support (CONFIG_NVMEM_IMX_SCU_OCOTP)
These options are enabled as built-in on the default ConnectCore 8X kernel configuration file.
Kernel driver
The OTP drivers are located at:
| File | Description |
|---|---|
OTP driver for the i.MX8X |
|
OTP driver for the i.MX8X SCU |
Device tree bindings
The device tree node for the OTP driver is defined in the common i.MX8QXP device tree file:
i.MX8QXP device tree
ocotp: ocotp {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,imx8qxp-ocotp", "syscon";
};OTP user space usage
The OTP words are accessible (read-only) through the sysfs at /sys/devices/platform/ocotp/imx-ocotp0/nvmem.
~# od -A x -x /sys/devices/platform/ocotp/imx-ocotp0/nvmem 000000 0000 0000 0008 0000 000b 0000 0000 0000 000010 0002 0000 0000 0000 0000 0000 0000 0000 000020 0000 0000 0000 0000 0000 0000 0000 0000 000030 0000 0000 0000 0000 0003 0000 000c 0000 000040 bc4a 57ac 180b 0314 0000 0000 0000 0000 000050 0000 0000 0000 0000 0000 0000 0000 0000 * 000190 0000 2800 0000 0000 0022 2600 0000 0000 0001a0 0000 0000 0000 0000 0680 0000 0788 0000 0001b0 0000 0000 0000 0000 0000 0000 0000 0000 0001c0 1001 5500 0974 0000 4320 4603 0978 0000 0001d0 bf00 4629 0804 5500 2340 41fc 0000 8800 0001e0 0000 0000 0000 0000 0000 0000 0000 0000 * 0002e0 bada bada bada bada bada bada bada bada * 000320 0000 0000 0000 0000 0000 0000 0000 0000 * 000400 0000 0000 2010 05c0 0000 0000 0000 0000 000410 0000 0000 0000 0000 0000 0000 0000 0000 * 000c40 5e33 8315 0000 0000 bada bada bada bada 000c50 0000 0000 0000 0000 0000 0000 0000 0000 * 0000c80
