The STMicroelectronics STM32MP25 CPU has three 10/100/1000 Ethernet MAC.

On the ConnectCore MP25 Development Kit:

  • Ethernet port 1 is connected to a 10/100/1000 Marvell 88E1512-A0-NNP2I000 PHY.

  • Ethernet port 2 is connected to a 10/100/1000 Marvell 88E1512-A0-NNP2I000 PHY.

The MAC address and serial number of the SOM are encoded in the data matrix on the SOM label.

Kernel configuration

You can manage the Ethernet driver and PHY device support through the following kernel configuration options:

  • STM32 Ethernet controller (DWMAC) (CONFIG_DWMAC_STM32)

  • PHY device support for Marvell (88E1XXX) (CONFIG_MARVELL_PHY)

These options are enabled as built-in on the default ConnectCore MP25 kernel configuration file.

Kernel driver

The drivers for the Ethernet interface are located at:

File Description

drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c

DWMAC driver

drivers/net/phy/marvell.c

Driver for Marvel PHY 88E1XXX

Device tree bindings and customization

The STM32MP25 Ethernet interface device tree binding is documented at Documentation/devicetree/bindings/net/stm32-dwmac.yaml. The Ethernet interface is defined in the STM32MP25 CPU and ConnectCore MP25 Development Kit device tree files.

Example: DWMAC on ConnectCore MP25 Development Kit

Definition of the DWMAC

STM32MP25 device tree
eth1: eth1@482c0000 {
	compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.10a";
	reg = <0x482c0000 0x4000>;
	reg-names = "stmmaceth";
	interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "macirq";
	clock-names = "stmmaceth",
			"mac-clk-tx",
			"mac-clk-rx",
			"ptp_ref",
			"ethstp",
			"eth-ck";
	clocks = <&rcc CK_ETH1_MAC>,
		<&rcc CK_ETH1_TX>,
		<&rcc CK_ETH1_RX>,
		<&rcc CK_KER_ETH1PTP>,
		<&rcc CK_ETH1_STP>,
		<&rcc CK_KER_ETH1>;
	st,syscon = <&syscfg 0x3000 0xffffffff>;
	snps,mixed-burst;
	snps,pbl = <2>;
	snps,txqos = <7>;
	snps,rxqos = <7>;
	snps,axi-config = <&stmmac_axi_config_1>;
	snps,tso;
	access-controllers = <&rifsc 60>;
	power-domains = <&CLUSTER_PD>;
	wakeup-source;
	status = "disabled";
	snps,mtl-rx-config = <&mtl_rx_setup_1>;
	snps,mtl-tx-config = <&mtl_tx_setup_1>;

	stmmac_axi_config_1: stmmac-axi-config {
		snps,wr_osr_lmt = <0x7>;
		snps,rd_osr_lmt = <0x7>;
		snps,blen = <0 0 0 0 16 8 4>;
	};

	mtl_rx_setup_1: rx-queues-config {
		snps,rx-queues-to-use = <2>;
		queue0 {};
		queue1 {};
	};

	mtl_tx_setup_1: tx-queues-config {
		snps,tx-queues-to-use = <4>;
		queue0 {};
		queue1 {};
		queue2 {};
		queue3 {};
	};
};

IOMUX configuration

STM32MP25 device tree
eth1_mdio_pins_a: eth1-mdio-0 {
	pins1 {
		pinmux = <STM32_PINMUX('F', 0, AF10)>; /* ETH_MDC */
		bias-disable;
		drive-push-pull;
		slew-rate = <2>;
	};
	pins2 {
		...
	};
};

eth1_mdio_sleep_pins_a: eth1-mdio-sleep-0 {
	pins1 {
		pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* ETH_MDC */
			 <STM32_PINMUX('F', 2, ANALOG)>; /* ETH_MDIO */
	};
};

eth1_rgmii_pins_a: eth1-rgmii-0 {
	pins1 {
		pinmux = <STM32_PINMUX('A', 15, AF10)>, /* ETH_RGMII_TXD0 */
			 <STM32_PINMUX('C', 1, AF10)>, /* ETH_RGMII_TXD1 */
			 <STM32_PINMUX('H', 10, AF10)>, /* ETH_RGMII_TXD2 */
			 <STM32_PINMUX('H', 11, AF10)>, /* ETH_RGMII_TXD3 */
			 <STM32_PINMUX('A', 13, AF10)>; /* ETH_RGMII_TX_CTL */
		bias-disable;
		drive-push-pull;
		slew-rate = <3>;
		st,io-retime = <1>;
		st,io-clk-edge = <1>;
	};
	pins2 {
		...
	};
	pins3 {
		...
	pins4 {
		pinmux = <STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */
		bias-disable;
	};
};

eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 {
	pins {
		pinmux = <STM32_PINMUX('A', 15, ANALOG)>, /* ETH_RGMII_TXD0 */
			 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_TXD1 */
			 <STM32_PINMUX('H', 10, ANALOG)>, /* ETH_RGMII_TXD2 */
			 <STM32_PINMUX('H', 11, ANALOG)>, /* ETH_RGMII_TXD3 */
			 <STM32_PINMUX('A', 13, ANALOG)>, /* ETH_RGMII_TX_CTL */
			 <STM32_PINMUX('H', 9, ANALOG)>, /* ETH_RGMII_CLK125 */
			 <STM32_PINMUX('C', 0, ANALOG)>, /* ETH_RGMII_GTX_CLK */
			 <STM32_PINMUX('F', 1, ANALOG)>, /* ETH_RGMII_RXD0 */
			 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_RXD1 */
			 <STM32_PINMUX('H', 12, ANALOG)>, /* ETH_RGMII_RXD2 */
			 <STM32_PINMUX('H', 13, ANALOG)>, /* ETH_RGMII_RXD3 */
			 <STM32_PINMUX('A', 11, ANALOG)>, /* ETH_RGMII_RX_CTL */
			 <STM32_PINMUX('A', 14, ANALOG)>; /* ETH_RGMII_RX_CLK */
	};
};

Ethernet enabling and PHY parameters

ConnectCore MP25 Development Kit device tree
&eth1 {
	status = "okay";
	pinctrl-0 = <&eth1_rgmii_pins_a &eth1_mdio_pins_a>;
	pinctrl-1 = <&eth1_rgmii_sleep_pins_a &eth1_mdio_sleep_pins_a>;
	pinctrl-names = "default", "sleep";
	phy-mode = "rgmii-id";
	max-speed = <1000>;
	phy-handle = <&phy1_eth1>;
	snps,ext-systime;

	/* ETH1 connected to the mdio bus ETH1_MDIO */
	mdio1 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";

		phy1_eth1: ethernet-phy@0 {
			compatible = "ethernet-phy-id0141.0dd0"; /* PHY ID for Marvell 88E1512 */
			reset-gpios =  <&gpiob 2 GPIO_ACTIVE_LOW>; /* ETH1_RST */
			reset-assert-us = <1000>;
			reset-deassert-us = <2000>;
			reg = <0>;
		};
	};
};

MAC addresses

The MAC address of the STM32MP25 Ethernet interface is programmed in the U-Boot environment (variable ethaddr) on the ConnectCore MP25 eMMC. The MAC address of the Ethernet interface is also printed on the module label. U-Boot writes the MAC address in the ethaddr environment variable into its respective device tree ethernet0 node under the local-mac-address property. For more information, see Environment variables.

Ethernet user space usage

In the Linux system, the Ethernet interface is known as ethX where X is a number, starting at 0, that indicates the interface index. The Ethernet (DWMAC) driver exposes device data through the sysfs at /sys/class/net/ethX. You can use NetworkManager to configure Ethernet settings such as IP and netmask.