The following table lists the U-Boot file associated with each ConnectCore 93 variant:
RAM size | SOC revision | U-Boot file | U-Boot defconfig |
---|---|---|---|
any |
A0 |
||
A1 |
Check your SOC revision and RAM size on the serial console boot log:
U-Boot SPL dub-2024.04-r2.2+g9218b07cddd+p0 (Feb 24 2025 - 15:03:54 +0000)
SOC: 0xa1009300
LC: 0x2040010
PMIC: PCA9451A
PMIC: Over Drive Voltage Mode
M33 prepare ok
Normal Boot
Trying to boot from BOOTROM
Boot Stage: Primary boot
image offset 0x0, pagesize 0x200, ivt offset 0x0
Load image from 0x52800 by ROM_API
NOTICE: TRDC init done
NOTICE: BL31: v2.10.0 (release):android-15.0.0_1.0.0-rc3-0-g1b27ee3ed-dirty
NOTICE: BL31: Built : 15:03:54, Feb 24 2025
U-Boot dub-2024.04-r2.2+g9218b07cddd+p0 (Feb 24 2025 - 15:03:54 +0000)
Reset Status: POR
CPU: NXP i.MX93(52) Rev1.1 A55 at 1700 MHz
CPU: Industrial temperature grade (-40C to 105C) at 40C
DRAM: 992 MiB
Core: 221 devices, 34 uclasses, devicetree: separate
MMC: FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... OK
[*]-Video Link 0 (1920 x 1080)
[0] lcd-controller@4ae30000, video
[1] dsi@4ae10000, video_bridge
[2] lt8912@48, panel
In: serial
Out: serial
Err: serial
Model: Digi ConnectCore 93 Development Kit
ConnectCore 93 SOM variant 0x01: 992 MiB LPDDR4, Wi-Fi, Bluetooth
Board version undefined, ID undefined
Boot: MMC0
BuildInfo:
- ELE firmware version 2.0.0-64d8ef47
flash target is MMC:0
Net: eth0: ethernet@428a0000 [PRIME]
Fastboot: Normal
Normal Boot
Hit any key to stop autoboot: 0
=>
NXP released two revisions of the SOC silicon: revision A0 and revision A1. See SOC revisions for more information. |
U-Boot might show less DRAM than the nominal. This is due to elements such as the secure monitor (OP-TEE) reserving part of the memory. |