Pulse-width modulation (PWM) is a technique that modifies the duty cycle of a pulsing signal to encode information or to control the amount of energy provided to a charge. The MCA implements pulse-width modulation in its firmware.
The MCA on the ConnectCore 8X system-on-module provides tree PWM controllers. Each controller has several channels and each channel maps to one MCA IO pin:
PWM controller | Number of channels | Channel | IO |
---|---|---|---|
PWM0 |
6 |
0 |
MCA_IO0 |
1 |
MCA_IO12 |
||
2 |
MCA_IO15 |
||
3 |
MCA_IO16 |
||
4 |
MCA_IO17 |
||
5 |
MCA_IO18 |
||
PWM1 |
2 |
0 |
MCA_IO5 |
1 |
MCA_IO6 |
||
PWM2 |
2 |
0 |
MCA_IO7 |
1 |
MCA_IO8 |
On the ConnectCore 8X:
-
All MCA PWM channels are available on the LGA pads.
-
PWM0 channel 0 is available on the castellated pads.
-
PWM1 channels 0 and 1 are available on the castellated pads.
-
PWM2 channels 0 and 1 are available on the castellated pads.
On the ConnectCore 8X SBC Pro:
-
PWM0 channel 1 is available on the expansion header but shared with BT_WAKEUP_HOST signal so it can only be used with non-wireless versions of the SOM.
-
PWM0 channel 4 is available on the expansion header.
-
PWM0 channel 5 is routed to USER_LED0.
-
PWM2 channels 0 and 1 are available on the expansion header.
See MCA I/O pads for a list of all available MCA IOs and their capabilities. |
Kernel configuration
You can manage the ConnectCore 8X MCA PWM driver support through the following kernel configuration option:
-
Digi MCA PWM support (
CONFIG_PWM_MCA
)
This option is enabled as built-in on the default ConnectCore 8X kernel configuration file.
Kernel driver
The driver for the ConnectCore 8X MCA PWM is located at:
File | Description |
---|---|
MCA PWM driver |
Device tree bindings and customization
The ConnectCore 8X MCA PWM interface is documented at Documentation/devicetree/bindings/pwm/digi,mca-pwm.txt
.
ConnectCore 8X MCA PWM interfaces
The common ConnectCore 8X device tree file contains entries for all the MCA PWM controllers:
mca_cc8x: mca@63 {
pwms {
compatible = "digi,mca-pwm";
#address-cells = <1>;
#size-cells = <0>;
mca_pwm0: pwm@0 {
reg = <0>;
pwm-channels = <6>;
#pwm-cells = <3>;
};
mca_pwm1: pwm@1 {
reg = <1>;
pwm-channels = <2>;
#pwm-cells = <3>;
};
mca_pwm2: pwm@2 {
reg = <2>;
pwm-channels = <2>;
#pwm-cells = <3>;
};
};
};
Using the MCA PWM channels
From sysfs
Each PWM interface is registered in the system as a standalone PWM controller.
The PWM interfaces appear under /sys/class/pwm
:
# ls -l /sys/class/pwm/
lrwxrwxrwx 1 root root 0 Oct 8 15:14 pwmchip0 -> ../../devices/platform/bus@5a000000/5a800000.i2c/i2c-0/0-0063/mca-pwm/pwm/pwmchip0
lrwxrwxrwx 1 root root 0 Oct 8 15:14 pwmchip10 -> ../../devices/platform/bus@56220000/56224000.pwm/pwm/pwmchip10
lrwxrwxrwx 1 root root 0 Oct 8 15:14 pwmchip6 -> ../../devices/platform/bus@5a000000/5a800000.i2c/i2c-0/0-0063/mca-pwm/pwm/pwmchip6
lrwxrwxrwx 1 root root 0 Oct 8 15:14 pwmchip8 -> ../../devices/platform/bus@5a000000/5a800000.i2c/i2c-0/0-0063/mca-pwm/pwm/pwmchip8
The PWM interfaces begin numbering with an index of 0. The indexes are calculated using the number of channels of the previous interface. On the example above (SBC Pro):
-
MCA PWM0 (6 channels) is
pwmchip0
-
MCA PWM1 (2 channels) is
pwmchip6
-
MCA PWM2 (2 channels) is
pwmchip8
-
{cpu-family} MIPI-DSI0 PWM (1 channel) is
pwmchip10
Check the number of channels of an interface by printing the value of npwm
:
# cat /sys/class/pwm/pwmchip8/npwm
2
To access one channel of a PWM interface, export the channel index. For example, for accessing channel 0 of MCA PWM2:
# echo 0 > /sys/class/pwm/pwmchip8/export
Now you can access the PWM channel and configure its settings:
# ls /sys/class/pwm/pwmchip8/pwm0/
capture duty_cycle enable period polarity power uevent
Period and duty cycle must be given in nanoseconds.
The maximum frequency of the MCA PWM is 1MHz (period = 1000ns). The minimum frequency of the MCA PWM is 100Hz (period = 10000000ns). |
For example, to configure a 100kHz signal with 20% duty cycle:
# echo 10000 > /sys/class/pwm/pwmchip8/pwm0/period
# echo 2000 > /sys/class/pwm/pwmchip8/pwm0/duty_cycle
Each MCA PWM controller can only have one frequency for all its channels. Changing the period for one channel affects the period of all the channels in that MCA PWM controller. You can only change the period of a channel if all the channels in that PWM controller are disabled. |
To enable the PWM signal:
# echo 1 > /sys/class/pwm/pwmchip8/pwm0/enable
The default polarity is normal
(active high for the duty cycle).
To invert the polarity:
# echo inversed > /sys/class/pwm/pwmchip8/pwm0/polarity
Using Digi APIx library from a C application
An example application called apix-pwm-example
is included in the dey-examples-digiapix recipe (part of dey-examples package) of meta-digi layer.
This application shows how to generate a PWM signal using Digi APIx library on the ConnectCore 8X platform.
Go to GitHub to see the application instructions and source code.
See PWM API for more information about the PWM APIx.
See also
-
Pulse-width Modulation (PWM) ({cpu-family} SOC PWMs)