The NXP i.MX91 Cortex-A55 has eight UART interfaces that can be used for serial communication with devices either directly or through level adapters.

You can use the RTS and CTS hardware flow control lines on all of the UART interfaces.

On the ConnectCore 91 system-on-module:

  • UART1 is connected to the Bluetooth chip (on module variants with Bluetooth).

  • UART3, UART6, and UART7 are available at the castellated pads (multiplexed with other functionality).

  • All eight UARTs (UART1..UART8) are available at LGA pads (multiplexed with other functionality).

On the ConnectCore 93 Development Kit:

  • UART1 is routed to an expansion connector, to be used only on modules with no Bluetooth chip (4-wires: RX/TX/RTS/CTS).

  • UART4 is routed to the XBee connector (4-wires: RX/TX/RTS/CTS).

  • UART6 is routed to the console connector (2-wires: RX/TX).

  • UART7 is routed to the mikroBUS™ connector (2-wires: RX/TX).

Some lines of UART4 and UART7 are multiplexed with other functionality through a group of jumpers on the ConnectCore 93 Development Kit. Make sure the appropriate jumpers are connected when using these UARTs on the ConnectCore 93 Development Kit.

See Hardware reference manuals for information on the jumper connections and the multiplexed functionality they select.

Kernel configuration

You can manage the UART support through the kernel configuration options:

  • Freescale lpuart serial port support (CONFIG_SERIAL_FSL_LPUART)

  • Console on Freescale lpuart serial port (CONFIG_SERIAL_FSL_LPUART_CONSOLE)

These options are enabled as built-in on the default ConnectCore 91 kernel configuration file.

Kernel driver

File Description

drivers/tty/serial/fsl_lpuart.c

Freescale LPUART driver

Device tree bindings and customization

The i.MX91 UART interface device tree binding is documented at Documentation/devicetree/bindings/serial/fsl-lpuart.yaml

Silicon revision A0 of the i.MX91 has defects on the DMA that affect the behavior of the LPUARTs. To avoid communication problems with the LPUARTs, disable the DMA on the device tree by adding the following lines to your LPUARTs, for instance:

&lpuart4 {
	/delete-property/dmas;
	/delete-property/dma-names;
};

Refer to [{XREF_hw-soc-revisions_r}] for information about the silicon revision of your module.

RS-485 support

RS-485 is a standard defining the electrical characteristics of drivers and receivers in balanced digital multipoint systems. RS-485 only specifies electrical characteristics of the generator and the receiver; it does not specify or recommend a communications protocol.

The i.MX91 serial driver includes support for the RS-485 standard. No specific kernel configuration is necessary to support RS-485 over the serial interface. The device tree bindings are documented at Documentation/devicetree/bindings/serial/rs485.yaml

RS-485 half-duplex needs the RX and TX lines for data communication and the RTS line to control the RS-485 transceiver to either drive output or receive input from outside the chip.

To enable RS-485 mode on a UART port, apply the following changes to the device tree node:

  • Add property linux,rs485-enabled-at-boot-time.

  • Optionally add property rs485-rts-active-high to define RTS line polarity as ACTIVE HIGH. Default polarity is ACTIVE LOW.

  • Optionally add property rs485-rx-during-tx to allow receiving data while sending data.

  • Optionally add property rs485-rts-delay = <a b> to define:

    • a: Delay in milliseconds between RTS line assertion and start of transmission.

    • b: Delay in milliseconds between end of transmission and RTS line de-assertion.

  • RTS line (output) to drive RS-485 direction:

    • To use the UART’s native RTS line, add boolean property fsl,uart-has-rtscts.

    • To use a regular GPIO as RTS line, add property rts-gpios with a GPIO reference. Use macros GPIO_ACTIVE_LOW or GPIO_ACTIVE_HIGH on this property to define the polarity of this GPIO.

Example: RS-485 on ConnectCore 93 Development Kit

By default, only UART7 on the ConnectCore 93 Development Kit device tree is configured in RS-485 mode:

  • UART7 is routed to J50 connector through an RS-485 transceiver with A and B differential lines.

  • RS485_RE#/DE = GPIO2_IO10 is routed to the RS-485 transceiver DE/#RE pins.

    ConnectCore 93 Development Kit device tree
    /*
 * RS485/mikroBUS UART
 * The uart of the RS485 and the mikroBUS interfaces is shared. Configure the
 * corresponding jumpers to select the desired functionality.
 */
&lpuart7 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart7>;
	linux,rs485-enabled-at-boot-time;
	digi,rts-gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>;
	/delete-property/dmas;
	/delete-property/dma-names;
	status = "okay";
};

[...]

	/* mikroBUS/RS485 uart */
	pinctrl_uart7: uart7grp {
		fsl,pins = <
			MX91_PAD_GPIO_IO09__LPUART7_RX                          0x31e
			MX91_PAD_GPIO_IO08__LPUART7_TX                          0x31e
			/* RS485_DE */
			MX91_PAD_GPIO_IO10__GPIO2_IO10                          0x31e
		>;
	};

UART user space usage

The i.MX91 UART bus driver exposes device data through the sysfs at /sys/class/tty/ttyLPN/, where N is the port index, starting at zero.

UART device interface

You can access i.MX91 UART devices from user space through the device node /dev/ttyLPN, where N is the port index, starting at zero.

For information about using the serial port from user space, see the Serial Programming Guide for POSIX Operating Systems.