The NXP i.MX8M Nano CPU has three SPI buses and a Flexible SPI interface with two ports than can operate as Quad-SPI.

On the ConnectCore 8M Nano system-on-module:

  • ECSPI1 and ECSPI2 are available (multiplexed with other functionality) on the castellated pads.

  • All three SPI ports are available (multiplexed with other functionality) on the LGA pads.

  • Quad-SPI A port is available on the LGA pads.

On the ConnectCore 8M Nano Development Kit:

  • The SPI3 interface is connected to an SPI CAN controller (MCP2517FD). See Controller Area Network (CAN) for more information.

  • None of the SPI buses are available on any connector of the ConnectCore 8M Nano Development Kit.

Kernel configuration

You can manage the SPI driver support through the kernel configuration option:

  • Freescale i.MX SPI controller (CONFIG_SPI_IMX)

This option is enabled as built-in on the default ConnectCore 8M Nano kernel configuration file.

Kernel driver

File Description

drivers/spi/spi-imx.c

i.MX SPI driver

Device tree bindings and customization

The i.MX8M Nano SPI interface device tree binding is documented at Documentation/devicetree/bindings/spi/fsl-imx-cspi.yaml.

The common i.MX8M Nano CPU device tree defines all the SPI ports. The platform device tree must:

  • Enable the required SPI port, by setting the status property to "okay".

  • Choose the chip selects using property cs-gpios and their number using property fsl,spi-num-chipselects.

  • Configure the IOMUX of the pads that will work as SPI port.

  • Add the SPI slave devices as children of the SPI bus node.

Example: SPI3 port (as master) on the ConnectCore 8M Nano Development Kit

ConnectCore 8M Nano Development Kit device tree
&ecspi3 {
	#address-cells = <1>;
	#size-cells = <0>;
	num-cs = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
	cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
	status = "okay";

	/* SPI slave devices come here */
};

[...]

&iomuxc {
	[...]

	pinctrl_ecspi3: ecspi3grp {
		fsl,pins = <
			MX8MN_IOMUXC_UART1_RXD_ECSPI3_SCLK		0x82
			MX8MN_IOMUXC_UART1_TXD_ECSPI3_MOSI		0x82
			MX8MN_IOMUXC_UART2_RXD_ECSPI3_MISO		0x82
		>;
	};

	pinctrl_ecspi3_cs: ecspi3cs {
		fsl,pins = <
			MX8MN_IOMUXC_UART2_TXD_GPIO5_IO25		0x40000
		>;
	};

	[...]
};

SPI user space usage

The SPI bus cannot be accessed directly from user space. Instead, it is accessed via the SPI client drivers.

Sample application

An example application called apix-spi-example is included in the dey-examples-digiapix recipe (part of dey-examples package) of the meta-digi layer. This application is an example of how to write data to an external EEPROM (24FC1026) and read it back using Digi APIx library on the ConnectCore 8M Nano platform.

Go to GitHub to see the application instructions and source code.

See SPI API for more information about the SPI APIx.

Quad-SPI

Quad-SPI bus cannot be used on the ConnectCore 8M Nano Development Kit out of the box. Quad-SPI interface lines conflict with the LVDS and HDMI interfaces. Besides, the ConnectCore 8M Nano Development Kit doesn’t contain any Quad-SPI slave device.

Digi Embedded Yocto includes a sample reference device tree overlay that enables the Quad-SPI bus to interface a NOR Flash memory. This device tree overlay disables all conflicting interfaces of the ConnectCore 8M Nano Development Kit.