The NXP {cpu-family} Cortex-A53 has four UART interfaces that can be used for serial communication with devices either directly or through level adapters.

You can use the RTS and CTS hardware flowcontrol lines on all of the UART interfaces.

The NXP {cpu-family} Cortex-M7 has one additional UART interface for use by the Cortex-M7 firmware.

On the ConnectCore 8M Nano system-on-module:

  • UART2 is connected to the Bluetooth chip (on modules with Bluetooth).

  • UART1, UART3, and UART4 are available for peripheral use.

  • Cortex-M7 UART0 is available only for use by the Cortex-M7 firmware.

The MCA in the ConnectCore 8M Nano system-on-module also supports one or more UARTs depending on the firmware version.

See MCA UART serial port for additional information on MCA UARTs.

On the ConnectCore 8M Nano Development Kit:

  • UART1 is routed to the console connector (two wires: RX/TX).

  • UART3 can be used as a four-wire RS-232 (RX/TX/RTS/CTS) on J45 connector or as RS-485 (RS485_A/RS485_B) on J26 connector.

    See RS-485 support for details on RS-485 configuration.

    To use UART3 as a four-wire RS-232 on the ConnectCore 8M Nano Development Kit, remove 0-ohm resistors R291, R292, and R359 to prevent conflicts from the RS-485 transceiver present on the board.

  • UART4 is routed to the XBee User connector.

Kernel configuration

You can manage the UART support through the kernel configuration options:

  • IMX serial port support (CONFIG_SERIAL_IMX)

  • Console on IMX serial port (CONFIG_SERIAL_IMX_CONSOLE)

Kernel driver

File Description

drivers/tty/serial/imx.c

IMX UART driver

Device tree bindings and customization

The {cpu-family} UART interface device tree binding is documented at Documentation/devicetree/bindings/serial/fsl-imx-uart.txt

RS-485 support

RS-485 is a standard defining the electrical characteristics of drivers and receivers in balanced digital multipoint systems. RS-485 only specifies electrical characteristics of the generator and the receiver; it does not specify or recommend a communications protocol.

The {cpu-family} serial driver includes support for the RS-485 standard. No specific kernel configuration is necessary to support RS-485 over the serial interface. The device tree bindings are documented at Documentation/devicetree/bindings/serial/rs485.txt

RS-485 half-duplex needs the RX and TX lines for data communication and the CTS line to control the RS-485 transceiver to either drive output or receive input from outside the chip.

In {cpu-family} CPUs, the CTS line is an output of the CPU that requests the transmitter to send data (effectively RTS). The RTS line is an input of the CPU that receives requests from receivers for stopping/resuming transmission (effectively CTS).

To enable RS-485 mode on a UART port, apply the following changes to the device tree node:

  • Add property linux,rs485-enabled-at-boot-time.

  • Optionally add property rs485-rts-active-high to define CTS line polarity as ACTIVE HIGH. Default polarity is ACTIVE LOW.

  • Optionally add property rs485-rx-during-tx to allow receiving data while sending data.

  • Optionally add property rs485-rts-delay = <a b> to define:

    • a: Delay in milliseconds between CTS line assertion and start of transmission.

    • b: Delay in milliseconds between end of transmission and CTS line de-assertion.

  • CTS line (output) to drive RS-485 direction:

    • To use the UART’s native CTS line, add boolean property fsl,uart-has-rtscts.

    • To use a regular GPIO as CTS line, add property rts-gpios with a GPIO reference. Use macros GPIO_ACTIVE_LOW or GPIO_ACTIVE_HIGH on this property to define the polarity of this GPIO.

Example: RS-485 on ConnectCore 8M Nano Development Kit

By default, only UART3 on the ConnectCore 8M Nano Development Kit device tree is configured in RS-485 mode:

  • UART3 is routed to J26 connector through an RS-485 transceiver with A and B differential lines.

    UART3 can be used as a four wires RS-232 (RX/TX/RTS/CTS) or as RS-485 (RS485_A/RS485_B). Configure uart3 node accordingly. RS-232 is disabled by default.

  • RS485_RE#/DE = GPIO5_IO8 is routed to the RS-485 transceiver #RE pin. Define this GPIO as the RS-485 RTS line with ACTIVE HIGH polarity in the rts-gpios device tree property.

    ConnectCore 8M Nano Development Kit device tree
    /* Expansion port/RS485 UART */
&uart3 {
	pinctrl-names = "default";
	assigned-clocks = <&clk IMX8MN_CLK_UART3>;
	assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;

	/* RS-485 mode (comment these lines to use this UART in RS232 mode) */
	pinctrl-0 = <&pinctrl_uart3_rs485>, <&pinctrl_uart3_rs485_re>;
	linux,rs485-enabled-at-boot-time;
	rs485-rts-active-high;
	rts-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
	/* Disable DMA on this port when using rs485 */
	/delete-property/dmas;
	/delete-property/dma-names;

	/*
	 * RS-232 mode (uncomment these lines to use this UART in RS232 mode).
	 * (R291, R292 and R359 on the DVK must be removed).
	 */
	//fsl,uart-has-rtscts;
	//pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
};

UART user space usage

The {cpu-family} UART bus driver exposes device data through the sysfs at /sys/class/tty/ttymxcN/, where N is the port index, starting at zero.

UART device interface

You can access {cpu-family} UART devices from user space through the device node /dev/ttymxcN, where N is the port index, starting at zero.

The MCA in the ConnectCore 8M Nano system-on-module also supports one or more UARTs depending on the firmware version. See MCA UART serial port for additional information on MCA UARTs.

For information about using the serial port from user space, see the Serial Programming Guide for POSIX Operating Systems.