The MIPI Display Serial Interface (MIPI-DSI) connects the LCDIF (LCD controller) to an external MIPI display or bridge interface.

The ConnectCore 8M Nano Development Kit includes two MIPI bridges that allow for different display options. Use the fourth switch of the S1 micro-switches to control which bridge the video signal is routed to:

  • S1.4 OFF routes the video signal to the LT8912 MIPI-to-HDMI bridge (default position)

  • S1.4 ON routes the video signal to the SN65DSI83 MIPI-to-LVDS bridge

    The Linux DRM subsystem will select the MIPI-to-HDMI bridge in the default images regardless of the position of S1.4. To select the MIPI-to-LVDS bridge, see Configure LVDS as default bridge.

Kernel configuration

You can manage the video support through the following kernel configuration options:

  • i.MX LCDIF core support (CONFIG_IMX_LCDIF_CORE)

  • i.MX LCDIF controller DRM driver (CONFIG_DRM_IMX_LCDIF)

  • Support for Samsung MIPI DSIM displays (CONFIG_DRM_IMX_SEC_DSIM)

These options are enabled as built-in on the default ConnectCore 8M Nano kernel configuration file.

Kernel driver

The driver for the video interface is located at:

File Description

drivers/gpu/imx/lcdif/lcdif-common.c

LCD controller driver

drivers/gpu/drm/imx/lcdif

LCDIF DRM drivers

drivers/gpu/drm/imx/sec_mipi_dsim-imx.c

Samsung MIPI-DSI DRM driver

Device tree bindings and customization

The i.MX8M Nano LCDIF controller is documented at Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt.

The i.MX8M Nano MIPI-DSI interface is documented at Documentation/devicetree/bindings/display/bridge/sec_dsim.txt.

The LCDIF controller and MIPI-DSI interface are defined in the i.MX8M Nano CPU device tree file.

Definition of the LCDIF and MIPI-DSI

i.MX8M Nano device tree
lcdif: lcd-controller@32E00000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx8mn-lcdif";
	reg = <0x0 0x32e00000 0x0 0x10000>;
	clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
		 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
		 <&clk IMX8MN_CLK_DISP_APB_ROOT>;
	clock-names = "pix", "disp-axi", "disp-apb";
	assigned-clocks = <&clk IMX8MN_CLK_DISP_PIXEL>,
			  <&clk IMX8MN_CLK_DISP_AXI>,
			  <&clk IMX8MN_CLK_DISP_APB>;
	assigned-clock-parents = <&clk IMX8MN_VIDEO_PLL1_OUT>,
				 <&clk IMX8MN_SYS_PLL2_1000M>,
				 <&clk IMX8MN_SYS_PLL1_800M>;
	assigned-clock-rate = <594000000>, <500000000>, <200000000>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&lcdif_resets>;
	power-domains = <&dispmix_pd>;
	status = "disabled";

	lcdif_disp0: port@0 {
		reg = <0>;

		lcdif_to_dsim: endpoint {
			remote-endpoint = <&dsim_from_lcdif>;
		};
	};
};

mipi_dsi: mipi_dsi@32E10000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx8mn-mipi-dsim";
	reg = <0x0 0x32e10000 0x0 0x400>;
	clocks = <&clk IMX8MN_CLK_DSI_CORE>,
		 <&clk IMX8MN_CLK_DSI_PHY_REF>;
	clock-names = "cfg", "pll-ref";
	assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>,
			  <&clk IMX8MN_CLK_DSI_PHY_REF>;
	assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
				 <&clk IMX8MN_VIDEO_PLL1_OUT>;
	assigned-clock-rates = <266000000>, <594000000>;
	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&mipi_dsi_resets>;
	power-domains = <&mipi_pd>;
	status = "disabled";

	port@0 {
		dsim_from_lcdif: endpoint {
			remote-endpoint = <&lcdif_to_dsim>;
		};
	};
};

IOMUX configuration

The MIPI-DSI interface uses dedicated pins. No IOMUX configuration is necessary.

Display options

The MIPI bridges available on the ConnectCore 8M Nano Development Kit are enabled with additional kernel and device tree configurations. You can find more information about each bridge here:

Use the video interface

When the video interface is available, a bootup logo displays on the screen. For XWayland images, a Weston desktop launches after Linux starts.

Play a video

To play a video using Gstreamer:

~# gplay-1.0 /tmp/myvideo.mp4