The Texas Instruments SN65DSI83 MIPI-to-LVDS bridge converts the i.MX8M Nano MIPI-DSI signal to one suitable for LVDS displays.
To use this bridge, set the S1.4 micro-switch to ON.
Kernel configuration
You can manage the SN65DSI83 support through the following kernel configuration option:
-
TI SN65DSI83 MIPI DSI to LVDS bridge (CONFIG_DRM_I2C_SN65DSI83)
This option is enabled as built-in on the default ConnectCore 8M Nano kernel configuration file.
Kernel driver
The driver for the SN65DSI83 bridge is located at:
| File | Description |
|---|---|
SN65DSI83 MIPI-to-LVDS core driver |
|
SN65DSI83 MIPI-to-LVDS bridge driver |
Device tree bindings and customization
The SN65DSI83 bridge is defined in the ConnectCore 8M Nano Development Kit device tree file.
Definition of the SN65DSI83
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
status = "okay";
dsi_lvds_bridge: sn65dsi84@2c {
compatible = "ti,sn65dsi83";
reg = <0x2c>;
ti,dsi-lanes = <4>;
ti,lvds-format = <1>;
ti,lvds-bpp = <24>;
ti,width-mm = <217>;
ti,height-mm = <136>;
enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&gpio3>;
interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lvds>;
status = "okay";
display-timings {
native-mode = <&lvds0_g101evn010>;
/* AUO G101EVN01.0 */
lvds0_g101evn010: timing@0 {
clock-frequency = <69000000>;
hactive = <1280>;
vactive = <800>;
hfront-porch = <120>;
hback-porch = <1>;
hsync-len = <8>;
vback-porch = <10>;
vfront-porch = <1>;
vsync-len = <6>;
hsync-active = <1>;
vsync-active = <1>;
de-active = <1>;
pixelclk-active = <0>;
};
/* Fusion 10" F10A-0102 */
lvds0_hsd101pfw2: timing@1 {
clock-frequency = <45000000>;
hactive = <1024>;
vactive = <600>;
hfront-porch = <120>;
hback-porch = <1>;
hsync-len = <8>;
vback-porch = <10>;
vfront-porch = <1>;
vsync-len = <6>;
hsync-active = <1>;
vsync-active = <1>;
de-active = <1>;
pixelclk-active = <0>;
};
};
port {
dsi_lvds_bridge_in: endpoint {
remote-endpoint = <&mipi_dsi_lvds_out>;
};
};
};
...
};
...
&mipi_dsi {
status = "okay";
...
port@2 {
mipi_dsi_lvds_out: endpoint {
remote-endpoint = <&dsi_lvds_bridge_in>;
};
};
};IOMUX configuration
The following IOMUX entry configures the associated enable and interrupt GPIO pins.
pinctrl_lvds: lvdsgrp {
fsl,pins = <
/* SN65DSI83 enable */
MX8MN_IOMUXC_NAND_ALE_GPIO3_IO0 0x19
/* SN65DSI83 interrupt */
MX8MN_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19
>;
};Configure LVDS as default bridge
Linux has no way of telling which bridge the MIPI-DSI interface is being routed to on the ConnectCore 8M Nano Development Kit board. Both the MIPI-to-LVDS and MIPI-to-HDMI bridges are enabled by default on the ConnectCore 8M Nano Development Kit device tree. Because of this, the Linux DRM subsystem will default to the MIPI-to-HDMI bridge and configure it instead of the MIPI-to-LVDS one, even if the S1.4 micro-switch is on.
To have Linux select the MIPI-to-LVDS bridge by default, make the following change to the device tree:
--- a/arch/arm64/boot/dts/digi/ccimx8mn-dvk-wb.dts
+++ b/arch/arm64/boot/dts/digi/ccimx8mn-dvk-wb.dts
@@ -407,7 +407,7 @@
reset-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
hpd-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
digi,dsi-lanes = <4>;
- status = "okay";
+ status = "disabled";
port {
lt8912_1_in: endpoint {