The NXP i.MX8M Nano CPU has five GPIO ports. Each port can generate and control 32 signals.

The MCA also features a number of GPIO pins (multiplexed with Analog-to-Digital Converter (ADC) functionality). See MCA I/O pads for a list of all available MCA IOs and their capabilities.

GPIOs on the ConnectCore 8M Nano platforms

  • On the ConnectCore 8M Nano system-on-module:

    • Many of the i.MX8M Nano GPIOs are available at the system-on-module, multiplexed with other functions (labeled GPIOx_IOy where x is the port and y is the GPIO pin). See Hardware reference manuals for information about GPIO pins and their multiplexed functionality.

    • 15 MCA GPIO pins are available (labeled MCA_IOx where x is the GPIO pin).

  • On the ConnectCore 8M Nano Development Kit, the expansion connectors allow direct access to some of the i.MX8M Nano GPIOs.

GPIOs on the SOM and carrier board are used for many purposes, such as:

  • Power enable line for transceivers

  • Reset line for controllers

  • LCD backlight control

  • Interrupt line

  • User LED

  • User button

Kernel configuration

You can manage the user space interface with GPIOs through the kernel configuration options:

  • /sys/class/gpio/…​ (sysfs interface) (CONFIG_GPIO_SYSFS)

This option is enabled as built-in on the default ConnectCore 8M Nano kernel configuration file.

Support for i.MX8M Nano GPIOs is automatically provided through the non-visible option CONFIG_GPIO_MXC.

Kernel driver

The driver for the i.MX8M Nano GPIO is located at:

File Description

drivers/gpio/gpio-mxc.c

i.MX8M Nano GPIO driver

Device tree bindings and customization

The i.MX8M Nano GPIO device tree binding is documented at Documentation/devicetree/bindings/gpio/fsl-imx-gpio.txt.

One GPIO controller is defined for each i.MX8M Nano GPIO port in the common i.MX8M Nano device tree file:

i.MX8M Nano device tree
	gpio1: gpio@30200000 {
		compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
		reg = <0x0 0x30200000 0x0 0x10000>;
		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};
 
[...]
 
	gpio5: gpio@30240000 {
		compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
		reg = <0x0 0x30240000 0x0 0x10000>;
		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

The ConnectCore 8M Nano device tree include file and the carrier board device tree files use the i.MX8M Nano GPIOs.

For example, on the ConnectCore 8M Nano, GPIO3_IO08 is used as the MCA interrupt line, and GPIO1_IO4 is used to activate internal circuitry during the MCA firmware update:

ConnectCore 8M Nano device tree
	mca_cc8m: mca@63 {
		compatible = "digi,mca-cc8m";
		reg = <0x63>;
		interrupt-parent = <&gpio3>;
		interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <2>;
		fw-update-gpio = <&gpio1 4 GPIO_ACTIVE_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_mca_cc8m>;
 
		[...]
};

For example, on the ConnectCore 8M Nano Development Kit, GPIO5_IO3 is used to reset the PHY of ENET1 Ethernet interface:

ConnectCore 8M Nano Development Kit device tree
&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1_gpio>,
		    <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	digi,mdio-lt-supply = <&reg_1v8_ext>;
	phy-supply = <&reg_3v3_eth0>;
	phy-reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <1>;
	digi,phy-reset-in-suspend;
	fsl,magic-packet;
	status = "okay";

	[...]
};

IOMUX configuration

You must configure the pads that are to be used as i.MX8M Nano GPIOs. See Pin multiplexing (IOMUX).

For GPIOs that are managed by other drivers, you must configure their pad IOMUX inside the driver node specific pinctrl-0 to work according to the specified interface functionalities.

On the ConnectCore 8M Nano example from above, mca_cc8m node configures pinctrl_mca_cc8m:

ConnectCore 8M Nano device tree
pinctrl_mca_cc8m: mcagrp {
	fsl,pins = <
		/* MCA_nINT */
		MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8	0x56
		/* MCA_FW_UPDATE */
		MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4	0x16
	>;
};

For GPIOs that are not associated with any interface or that can’t be handled by a driver, see Configure independent pin IOMUX and pad control. The following external pads are configured as GPIOs on the default device tree:

  • On the ConnectCore 8M Nano Development Kit J46 expansion connector:

    Pad Signal GPIO

    1

    GPIO1_IO10

    GPIO1_IO10

    2

    GPIO1_IO11

    GPIO1_IO11

    3

    GPIO1_IO13

    GPIO1_IO13

    4

    GPIO1_IO14

    GPIO1_IO14

    5

    GPIO1_IO15

    GPIO1_IO15

  • On the ConnectCore 8M Nano Development Kit J48 expansion connector:

    Pad Signal GPIO

    5

    EXP_I2C_IRQ_N

    GPIO5_IO27

    7

    EXP_I2C_GPIO

    GPIO5_IO26

  • On the ConnectCore 8M Nano Development Kit user LED 3:

    Pad Signal GPIO

    1

    USER_LED3

    GPIO2_IO19

  • On the ConnectCore 8M Nano Development Kit user button 2:

    Pad Signal GPIO

    1

    USER_BUTTON2

    GPIO2_IO20

Using the GPIOs

You can access the GPIOs from the sysfs. See the Linux kernel documentation at Documentation/gpio/sysfs.txt.

Calculate the Linux GPIO number of a GPIO pin

For each GPIO controller entry on the device tree, Linux creates an entry /sys/class/gpio/gpiochipN, where N is an integer number starting at 0, with the following read-only attributes:

  • base: same as N, the first GPIO managed by this chip

  • label: provided for diagnostics (not always unique)

  • ngpio: the number of GPIOs this controller manages (from N to N + ngpio - 1)

GPIOs on the ConnectCore 8M Nano system-on-module

Every GPIO port of the i.MX8M Nano CPU is a different GPIO controller and thus has its own /sys/class/gpio/gpiochipN entry on the sysfs.

On the default ConnectCore 8M Nano system-on-module device tree, the i.MX8M Nano CPU’s GPIO ports are probed first:

  • PORT1: /sys/class/gpio/gpiochip0

  • PORT2: /sys/class/gpio/gpiochip32

  • PORT3: /sys/class/gpio/gpiochip64

  • PORT4: /sys/class/gpio/gpiochip96

  • PORT5: /sys/class/gpio/gpiochip128

Calculate the Linux GPIO number for a certain GPIO pin by adding the GPIO pin index to the port base index. For instance:

i.MX8M Nano GPIO2_IO4 (port 2, pin 4) is: 32 + 4 = 36

Since the i.MX8M Nano CPU has five ports, all of which have 32 pins, the following formula also applies to i.MX8M Nano CPU GPIOs (without requiring the user to know the GPIO base of each port):

\$"LinuxGPIO_num" = ("<port_index>" - 1) * 32 + "<gpio_pin>"\$

For example, i.MX8M Nano GPIO2_IO4 (port 2, pin 4) translates to:

\$(color(red)(2) - 1) * 32 + color(red)(4) = 36\$

Example: write from sysfs

The ConnectCore 8M Nano Development Kit has GPIO5_IO26 on the J48 expansion connector. To drive this GPIO as an ouput:

  1. Calculate the Linux GPIO number:

    \$"GPIO5_IO26" -> (color(red)(5) - 1) * 32 + color(red)(26) = 154\$

  2. Request the GPIO:

    ~# echo 154 > /sys/class/gpio/export

  3. Configure the GPIO as output:

    ~# echo out > /sys/class/gpio/gpio154/direction

  4. Drive the GPIO high:

    ~# echo 1 > /sys/class/gpio/gpio154/value

  5. Drive the GPIO low:

    ~# echo 0 > /sys/class/gpio/gpio154/value

  6. When you are done using the GPIO, free it with:

    ~# echo 154 > /sys/class/gpio/unexport

Sample application

An example application called apix-gpio-example is included in the dey-examples-digiapix recipe (part of dey-examples package) of meta-digi layer. This application shows how to manage GPIO lines using the Digi APIx library on the ConnectCore 8M Nano platform.

Go to GitHub to see the application instructions and source code.

See GPIO API for more information about the GPIO APIx.

See MCA General Purpose Input/Output (GPIO) for additional information on MCA GPIOs.