Video

lcdif: lcdif@32e00000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx8mm-lcdif";
	reg = <0x32e00000 0x10000>;
	clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
		 <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
		 <&clk IMX8MM_CLK_DISP_APB_ROOT>;
	clock-names = "pix", "disp-axi", "disp-apb";
	assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
			  <&clk IMX8MM_CLK_DISP_AXI>,
			  <&clk IMX8MM_CLK_DISP_APB>;
	assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
				 <&clk IMX8MM_SYS_PLL2_1000M>,
				 <&clk IMX8MM_SYS_PLL1_800M>;
	assigned-clock-rate = <594000000>, <500000000>, <200000000>;
	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	lcdif-gpr = <&dispmix_gpr>;
	resets = <&lcdif_resets>;
	power-domains = <&dispmix_pd>;
	status = "disabled";

	lcdif_disp0: port@0 {
		reg = <0>;

		lcdif_to_dsim: endpoint {
			remote-endpoint = <&dsim_from_lcdif>;
		};
	};
};

mipi_dsi: mipi_dsi@32e10000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx8mm-mipi-dsim";
	reg = <0x32e10000 0x400>;
	clocks = <&clk IMX8MM_CLK_DSI_CORE>,
		 <&clk IMX8MM_CLK_DSI_PHY_REF>;
	clock-names = "cfg", "pll-ref";
	assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
			  <&clk IMX8MM_CLK_DSI_PHY_REF>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
				 <&clk IMX8MM_CLK_24M>;
	assigned-clock-rates = <266000000>, <12000000>;
	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
	dsi-gpr = <&dispmix_gpr>;
	resets = <&mipi_dsi_resets>;
	power-domains = <&mipi_pd>;
	status = "disabled";

	port@0 {
		dsim_from_lcdif: endpoint {
			remote-endpoint = <&lcdif_to_dsim>;
		};
	};
};