The NXP {cpu-family} CPU has one PCI Express (PCIe) hardware module that can either be configured to act as a root complex or a PCI Express endpoint. PCI Express is a third-generation I/O interconnect targeting low-cost, high-volume, multi-platform interconnection.
PCIe includes the following cores:
-
PCIe dual mode (DM) core
-
PCIe root complex (RC) core
-
PCIe endpoint (EP) core
The BSP configures the PCIe port to act as Root Complex (RC).
On the ConnectCore 8M Mini system-on-module:
-
The PCIe bus is available on the LGA pads.
On the ConnectCore 8M Mini Development Kit:
-
The PCIe port is available in the PCIe mini card connector J19.
Kernel configuration
You can manage the PCIe driver support through the kernel configuration option:
-
Freescale i.MX6/7/8 PCIe controller (
CONFIG_PCI_IMX6
)
This option is enabled as built-in on the default ConnectCore 8M Mini kernel configuration file.
Kernel driver
The PCIe bus driver for the ConnectCore 8M Mini system-on-module is located at drivers/pci/controller/dwc/pci-imx6.c
.
Device tree bindings and customization
The {cpu-family} PCIe interface device tree binding is documented at Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
.
Example: PCIe (Mini card) on the ConnectCore 8M Mini Development Kit
Definition of the PCIe bus
pcie0: pcie@33800000 {
compatible = "fsl,imx8mm-pcie", "snps,dw-pcie";
reg = <0x33800000 0x400000>,
<0x1ff00000 0x80000>;
reg-names = "dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
num-lanes = <1>;
num-viewport = <4>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
interrupt-names = "msi", "dma";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
fsl,max-link-speed = <2>;
power-domains = <&pcie_pd>;
resets = <&src IMX8MQ_RESET_PCIEPHY>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
reset-names = "pciephy", "apps", "clkreq", "turnoff";
fsl,imx7d-pcie-phy = <&pcie_phy>;
status = "disabled";
};
PCIe port on the ConnectCore 8M Mini Development Kit
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
disable-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>;
wake-gpio = <&gpio3 21 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
<&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
ext_osc = <1>;
status = "okay";
};
IOMUX configuration
The ConnectCore 8M Mini Development Kit assembles a PCIe Mini card connector. Three GPIOs of the ConnectCore 8M Mini SOM are routed to the PCIe connector:
-
GPIO3_IO20: PCIe disable line
-
GPIO3_IO21: PCIe wake line
-
GPIO3_IO23: PCIe reset line
/* PCIE (Mini Card) */
pinctrl_pcie0: pcie0grp {
fsl,pins = <
/* Disable GPIO */
MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41
/* Reset GPIO */
MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x41
/* Wake GPIO */
MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x41
>;
};