Ethernet

fec1: ethernet@30be0000 {
	compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
	reg = <0x30be0000 0x10000>;
	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
		 <&clk IMX8MM_CLK_ENET1_ROOT>,
		 <&clk IMX8MM_CLK_ENET_TIMER>,
		 <&clk IMX8MM_CLK_ENET_REF>,
		 <&clk IMX8MM_CLK_ENET_PHY_REF>;
	clock-names = "ipg", "ahb", "ptp",
			"enet_clk_ref", "enet_out";
	assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
			  <&clk IMX8MM_CLK_ENET_TIMER>,
			  <&clk IMX8MM_CLK_ENET_REF>,
			  <&clk IMX8MM_CLK_ENET_TIMER>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
				 <&clk IMX8MM_SYS_PLL2_100M>,
				 <&clk IMX8MM_SYS_PLL2_125M>;
	assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
	fsl,num-tx-queues = <3>;
	fsl,num-rx-queues = <3>;
	nvmem-cells = <&fec_mac_address>;
	nvmem-cell-names = "mac-address";
	nvmem_macaddr_swap;
	stop-mode = <&gpr 0x10 3>;
	fsl,wakeup_irq = <2>;
	status = "disabled";
};

pinctrl_fec1_gpio: fec1gpiogrp {
	fsl,pins = <
		/* PHY reset */
		MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3		0x19
		/* PHY interrupt */
		MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2	0x19
	>;
};

pinctrl_fec1: fec1grp {
	fsl,pins = <
		MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x3
		MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO	0x3
		MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
		MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
		MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
		MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
		MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
		MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
		MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
		MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
		MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
		MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
		MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
		MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
	>;
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1_gpio>,
		    <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	digi,mdio-lt-supply = <&reg_1v8_ext>;
	phy-supply = <&reg_3v3_eth0>;
	phy-reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <1>;
	digi,phy-reset-in-suspend;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			at803x,eee-disabled;
			at803x,vddio-1p8v;
		};
	};
};