Pulse-width modulation (PWM) is a technique that modifies the duty-cycle of a pulsing signal to encode information or to control the amount of energy provided to a charge.
On the ConnectCore 8M Mini system-on-module:
-
Four PWM signals (from PWM1 to PWM4) are available from the {cpu-family} system-on-chip (multiplexed with other signals).
On the ConnectCore 8M Mini Development Kit:
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PWM1 is available at EXP_I2C_SDA on the J48 expansion connector. PWM1 is disabled by default due to conflicts with I2C4.
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PWM2, PWM3, and PWM4 are connected to the J46 expansion connector on pins 7, 9, and 4 respectively. PWM3 and PWM4 are disabled by default due to conflicts with USB-OTG2 power enable and overcurrent detect respectively.
This chapter describes the PWM channels from the CPU. See MCA Pulse Width Modulation (PWM) for information about the MCA PWM controllers. |
Kernel configuration
You can manage the {cpu-family} PWM driver support through the following kernel configuration option:
-
i.MX27 PWM support (
CONFIG_PWM_IMX27
)
This option is enabled as built-in on the default ConnectCore 8M Mini kernel configuration file.
Kernel driver
The driver for the {cpu-family} PWM is located at:
File | Description |
---|---|
PWM driver |
Device tree bindings and customization
The {cpu-family} PWM interface is documented at Documentation/devicetree/bindings/pwm/imx-pwm.txt
.
{cpu-family} PWM interfaces
The common {cpu-family} CPU device tree file contains entries for all the PWM channels:
pwm1: pwm@30660000 {
compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
reg = <0x30660000 0x10000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
<&clk IMX8MM_CLK_PWM1_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
status = "disabled";
};
pwm2: pwm@30670000 {
compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
reg = <0x30670000 0x10000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
<&clk IMX8MM_CLK_PWM2_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
status = "disabled";
};
pwm3: pwm@30680000 {
compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
reg = <0x30680000 0x10000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
<&clk IMX8MM_CLK_PWM3_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
status = "disabled";
};
pwm4: pwm@30690000 {
compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
reg = <0x30690000 0x10000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
<&clk IMX8MM_CLK_PWM4_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
status = "disabled";
};
IOMUX configuration
You must configure the pads that are to be used as {cpu-family} PWMs. See Pin multiplexing (IOMUX).
{cpu-family} pads should only have one IOMUX configuration. Remove other configurations for those pads, like GPIO, when configuring them as PWMs. |
The default device tree enables PWM2 available on the ConnectCore 8M Mini Development Kit J46 expansion connector:
-
PWM2 corresponds to pad GPIO1_IO13
-
PWM3 corresponds to pad GPIO1_IO14 (disabled by default due to conflicts with USB-OTG2 power enable)
-
PWM4 corresponds to pad GPIO1_IO15 (disabled by default due to conflicts with USB-OTG2 overcurrent detect)
Depending on the frequency of the PWM signal and the hardware around it, you must carefully select the pad settings (the numerical values following the IOMUX definition on the device tree).
See Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt
for information about the different values.
Also see the NXP application note AN5078 Influence of pin setting on system function and performance for additional information.
Using the PWM channels
You can access the PWM channels from your Android application. See PWM API for more information about the PWM APIx.
Sample application
The PWM Sample Application demonstrates the usage of the PWM API. In this example you can list all the available PWM chips and channels and configure the different PWM parameters.
Go to GitHub to see the application instructions and source code.