Peripheral Component Interconnect (PCI)

The NXP i.MX6 CPU has one PCI Express (PCIe) hardware module that can either be configured to act as a root complex or a PCIe endpoint. PCI Express (PCIe) is a third-generation I/O interconnect targeting low-cost, high-volume, multi-platform interconnection.

PCI Express includes the following cores:

PCI Express dual mode (DM) core
PCI Express root complex (RC) core
PCI Express endpoint (EP) core

The Linux BSP only supports the PCIe port acting as root complex.

Kernel configuration

You can manage the PCIe driver support through the kernel configuration option

PCI host controller drivers (CONFIG_PCI_IMX6)

This option is enabled as built-in on the default ConnectCore 6 SBC kernel configuration file.

Platform driver mapping

The PCIe bus driver for the ConnectCore 6 system-on-module is located at drivers/pci/host/pci-imx6.c.

Device tree bindings and customization

The i.MX6 PCIe interface device tree binding is documented at Documentation/devicetree/bindings/pci/fsl%2Cimx6q-pcie.txt.

The PCIe interface is defined in the i.MX6 CPU, ConnectCore 6 system-on-module, and ConnectCore 6 SBC device tree files.

Example: PCIe

Definition of the bus

Common i.MX6 device tree

pcie: pcie@0x01000000 {
        compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
        reg = <0x01ffc000 0x4000>, <0x01f00000 0x80000>;
        reg-names = "dbi", "config";
        #address-cells = <3>;
        #size-cells = <2>;
        device_type = "pci";
        ranges = <0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
                  0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
        num-lanes = <1>;
        interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "msi";
        #interrupt-cells = <1>;
        interrupt-map-mask = <0 0 0 0x7>;
        interrupt-map = <0 0 0 1 &intc 0 123 IRQ_TYPE_LEVEL_HIGH>,
                        <0 0 0 2 &intc 0 122 IRQ_TYPE_LEVEL_HIGH>,
                        <0 0 0 3 &intc 0 121 IRQ_TYPE_LEVEL_HIGH>,
                        <0 0 0 4 &intc 0 120 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clks IMX6QDL_CLK_PCIE_REF_125M>,
             <&clks IMX6QDL_CLK_SATA_REF_100M>,
             <&clks IMX6QDL_CLK_LVDS1_GATE>, <&clks IMX6QDL_CLK_PCIE_AXI>;
        clock-names = "pcie_phy", "ref_100m", "pcie_bus", "pcie";
        status = "disabled";
};

IOMUX configuration

The ConnectCore 6 SBC assembles a PCIe connector. Three GPIOs of the i.MX6 system-on-chip are routed to the PCIe connector:

GPIO1_4: PCIe disable line
GPIO7_7: PCIe wake line
GPIO7_8: PCIe reset line

The ConnectCore 6 SBC configures the IOMUX for these three GPIOs.

ConnectCore 6 SBC device tree

pcie {
        pinctrl_pcie: pcie {
            fsl,pins = <
                MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x80000000
                MX6QDL_PAD_GPIO_4__GPIO1_IO04   0x80000000
                MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000
            >;
        };
};

Note The i.MX6 PCIe driver only supports the reset line, not the wake or disable lines.

Bus enabling and customization

ConnectCore 6 SBC device tree

&pcie {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_pcie>;
    reset-gpio = <&gpio7 8 0>;
    wake-up-gpio = <&gpio7 7 0>;  /* not used by driver */
    disable-gpio = <&gpio1 4 0>;  /* not used by driver */
    vin-supply = <&ldo6>;
    status = "okay";
};